1. Field of the Invention
The present invention is generally in the field of semiconductor circuits. More particularly, the present invention is in the field of random access memory (RAM) cells and arrays.
2. Related Art
The microprocessor, the heart of consumer electronic devices such as personal computers and personal digital assistants (PDA), continues to follow Moore""s Law by doubling in speed approximately every eighteen months. Similarly, digital signal processors (DSP) utilized, for example, in broadband networks and digitized imaging applications, also continue to increase in speed. As a result, there is a continually increasing need for random access memory (RAM) arrays to provide increased access to the data required by these microprocessors and DSPs. Additionally, as the electronic devices that include the above microprocessors and DSPs continually decrease in size, there is also an increasing demand for RAM arrays that are smaller in size. Thus, RAM manufacturers are challenged to meet the demand for RAM arrays that provide increased data access and also take up less space. Further, as the demand for inexpensive consumer electronic devices continues to increase, RAM manufacturers face the additional challenge of reducing the cost of RAM arrays utilized in the consumer electronic devices.
By way of background, a RAM array comprises a large number of individual RAM cells. Data in the RAM array can be accessed or modified through one or more read or write ports. One approach used by RAM manufacturers to increase access to the data stored in the RAM cells is to increase the number of ports interfacing with the RAM array and allow the ports to be simultaneously read in a RAM read operation. U.S. Pat. No. 6,104,654, issued on Aug. 15, 2000, titled xe2x80x9cHigh Speed Sensing of Dual Port Static RAM Cellxe2x80x9d discloses a two port RAM array that allows data stored in the RAM array to be simultaneously read at two different ports.
In another approach, RAM manufacturers have provided a four port RAM array that allows data stored in the RAM array to be simultaneously read at four different ports. Each port in the four port RAM array is accessed by enabling a pair of access transistors in a RAM cell which couple the RAM cell to bit lines. The bit lines on each side of the RAM cell are coupled to the inputs of a differential sense amplifier. A change in voltage on the bit lines is recognized by the differential sense amplifier, and the data stored in the xe2x80x9cfour port RAM cellxe2x80x9d is outputted by the differential sense amplifier. Although the conventional four port RAM cell described above allows data to be simultaneously read at four ports, eight access transistors must be enabled in the conventional four port RAM cell to provide access to all four ports in the RAM array. As a result, the conventional xe2x80x9cfour port RAM cellxe2x80x9d has an undesirably large size.
Thus, there is a need in the art for an improved four port RAM cell. In particular, there is a need in the art for an improved four port RAM cell having a reduced size compared to a conventional four port RAM cell.
The present invention is directed to an improved four port RAM cell. The present invention addresses and resolves the need in the art for a four port RAM cell having a reduced size compared to a conventional four port RAM. Moreover, the present invention""s four port RAM has other significant advantages resulting from its unique design which will be discussed in the detailed description section below.
According to one exemplary embodiment of the invention, a RAM array includes at least one RAM cell comprising a first access transistor driven by a first word line. When the first access transistor is turned on, it couples the RAM cell to a first bit line. The first bit line is connected to a single-ended sense amplifier such as an inverter. Similarly, the RAM cell comprises second, third, and fourth access transistors driven by respectively second, third, and fourth word lines. When the respective access transistors are turned on, they couple the RAM cell to respectively second, third, and fourth bit lines. The bit lines are connected to respective single-ended sense amplifiers such as inverters.
In one exemplary embodiment, each of the first, second, third, and fourth access transistors is an NFET. The first, second, third, and fourth bit lines are coupled to respectively first, second, third, and fourth precharge transistors. In one embodiment, the precharge transistors are NFETs, while in an alternative embodiment the precharge transistors are PFETs.
The invention""s unique RAM cell results in a significant reduction in the number of RAM array transistors which results in a significantly smaller RAM array area, thus resulting in a reduced manufacturing cost. Moreover, the invention""s unique RAM cell results in a substantially lower word line capacitance since each word line is loaded with half as many access transistors as compared to a word line in a conventional RAM array. The significant lowering of the word line capacitance results in faster word lines, lower power consumption, and lower noise induced on the RAM array bit lines. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.